SLVS-EC Rx IP
Next generation Sony CMOS image sensor interface
Today Sony CMOS image sensors and Intel FPGAs are used in nearly all machine vision cameras, with Sony SLVS-EC the interface of choice to handle high-speed, long-distance communications between the two. It has become especially popular because it uses an embedded clock technology that’s tolerant of lane-to-lane skew.
Now, with our SLVS-EC Rx IP, Macnica Vision is offering an intellectual property package that makes board-level design for SLVS-EC very easy. It’s the toolkit you need for faster, better, easier and more profitable camera design.
- Compliant with SLVS-EC Specification Version 1.2/2.0
- Available both for Intel and Xilinx FPGAs
- Supports various functions defined by the SLVS-EC Link layer (Intel FPGA PCS/PMA is used as Physical layer for Intel implementation)
- Supports Byte-to-Pixel conversion for various lane-configurations
- Supports Header analysis and Payload error detection
|Number of Lanes||1, 2, 4, 6, 8|
|Baud Grade||1, 2, 3*|
|Bit per Pixel||8, 10, 12, 14, 16|
|Dynamic Mode Change||Supported|
|Multiple Stream||If needed|
* Baud Grade 3 is supported by only after 10 series.
* CRC: The operating frequency may not be achievable depending on the speed grade, number of lanes, and other factors of the FPGA used.
* Please contact Macnica sales department about unsupported functions and limitations.
- Intel Cyclone V GX
- Intel Cyclone V SX (v1.2)
- Intel Cyclone 10 GX
- Intel Arria 10 GX
- Intel Arria 10 SX (v1.2/2.0)
- Xilinx Artix-7 (ECC not supported)
- Xilinx Kintex-7
- Xilinx Kintex Ultrascale
- Xilinx Kintex Ultrascale+
- Microchip PolarFire (Planning)
* Please contact Macnica sales department about other devices.
- Encrypted RTL (Verilog HDL)
- Reference design
- Simulation environment (For ModelSim)
- User's manual, Reference manual, Simulation manual
* Please contact Macnica sales department about other deliverables.
Device Resource Utilization
Resource Utilization for 8 lane full configuration (including both Transceiver and IP)
|Items||Intel Cyclone® V GX||Intel Arria® 10 GX|
|w/o ECC||w/ECC||w/o ECC||w/ECC|
|Total block memory bits||4096||13312||2560||11776|
* The above values are estimated resource utilization of the IP and Transceivers. They may vary depending on your system configuration.
Evaluation / Demonstration
This IP can be evaluated and demonstrated using our EasyMVC Machine Vision Camera Development Kit.