SLVS-EC Rx IP

Image Sensor Interface

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SLVS-EC Rx IP

Next generation Sony CMOS image sensor interface

Today Sony CMOS image sensors and Intel FPGAs are used in nearly all machine vision cameras, with Sony SLVS-EC the interface of choice to handle high-speed, long-distance communications between the two. It has become especially popular because it uses an embedded clock technology that’s tolerant of lane-to-lane skew.

Now, with our SLVS-EC Rx IP, Macnica Vision is offering an intellectual property package that makes board-level design for SLVS-EC very easy. It’s the toolkit you need for faster, better, easier and more profitable camera design.

Features

  • Compliant with SLVS-EC Specification Version 1.2/2.0
  • Available both for Intel and Xilinx FPGAs
  • Supports various functions defined by the SLVS-EC Link layer (Intel FPGA PCS/PMA is used as Physical layer for Intel implementation)
  • Supports Byte-to-Pixel conversion for various lane-configurations
  • Supports Header analysis and Payload error detection

Specifications

FunctionDescription
Number of Lanes1, 2, 4, 6, 8
Baud Grade1, 2, 3*
Bit per Pixel8, 10, 12, 14, 16
CRCLimited*
ECCOption 1
Embedded DataSupported
Dynamic Mode ChangeSupported
Multiple StreamIf needed

* Baud Grade 3 is supported by only after 10 series.

* CRC: The operating frequency may not be achievable depending on the speed grade, number of lanes, and other factors of the FPGA used.

* Please contact Macnica sales department about unsupported functions and limitations.

Supported Devices

  • Intel Cyclone V GX
  • Intel Cyclone 10 GX
  • Intel Arria 10 GX
  • Xilinx Artix-7 (ECC not supported)
  • Xilinx Kintex-7
  • Xilinx Kintex Ultrascale
  • Xilinx Kintex Ultrascale+
  • Microchip PolarFire (Planning)

* Please contact Macnica sales department about other devices.

Deliverables

  • Encrypted RTL (Verilog HDL)
  • Reference design
  • Simulation environment (For ModelSim)
  • User's manual, Reference manual, Simulation manual

* Please contact Macnica sales department about other deliverables.

Device Resource Utilization

Resource Utilization for 8 lane full configuration (including both Transceiver and IP)

ItemsIntel Cyclone® V GXIntel Arria® 10 GX
w/o ECCw/ECCw/o ECCw/ECC
ALMs4711824239307555
Total Registers4328666437786079
Total block memory bits409613312256011776

*  The above values are estimated resource utilization of the IP and Transceivers. They may vary depending on your system configuration.

Evaluation / Demonstration

This IP can be evaluated and demonstrated using our EasyMVC Machine Vision Camera Development Kit.

Downloads

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