GigE Vision Device Package with IEEE1588
High-speed image data transfer complying with the GigE Vision standard
Now you can develop GigE Vision-compliant products (both 1-gig and 10-gig) much more quickly and economically using this advanced intellectual property package from Macnica Vision.
The GigE Vision Device Package includes everything you need to transfer image data from a camera or image sensor to other devices over Gigabit or 10-Gigabit Ethernet networks in real-time.
It’s perfect for the design and manufacturing of highly reliable, high-resolution machine vision cameras, medical imaging systems, and other devices.
- Highly reliable, high-precision image transmission using the GigE Vision and 10GigE Vision protocols
- 995 Mbps or 9.5 Gbps maximum effective transfer rate
- Comprehensive reference environment
- GigE Vision Compliant, certified by the Automated Imaging Association (AIA)
- Interoperability qualified with various GenICam application vendors
- Supports IEEE1588 PTP (Precision Time Protocol) as Master and Slave
- Compliant with GigE Vision Standard Version 1.2/Version 2.0
- Supports IEEE1588-2008 PTP
- Compliant with EMVA GenICam Standard Version 3.0.1
- Supports Packet Re-transmission
- Other functions
- Chunk data transfer, GigE Vision action commands, Timestamp, Packet delay
- Image data (RGB, YUV, etc.) and RAW data transfer
- 1GigE: Intel Cyclone V
- 10GigE: Intel Cyclone 10 GX
* Please contact Macnica sales department about other devices.
- Encrypted RTL (Verilog HDL)
- GigE Vision Device FW Library for Nios II processors
- Reference environment (sample hardware design, firmware application)
- User’s manual
* Please contact Macnica sales department about other deliverables.
Device Resource Utilization
- Cyclone V (1Gbps)
- Logic utilization (in ALMs) : 20,749.5
- Total registers: 37,430
- Total block memory (M10Ks): 233
- DSP Blocks: 14
- Cyclone 10 GX (10Gbps)
- Logic utilization (in ALMs) : 15,085.5
- Total registers: 37,467
- Total block memory (M10Ks): 56
- DSP Blocks: 9
* The values in the above table are based on an implementation example. There may be some variation depending on the user’s system configuration.
System Block Diagram